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| # | Company | Amount | Rank | Status |
|---|---|---|---|---|
| 1 | 1₹9.4 LAccepted-AOC 21 7TH MAIN 1ST BLOCK KORAMANGALA BANGALORE 560034 | BANGALORE | BENGALURU URBAN | KARNATAKA | 560034 | ₹9.4 L | 1 | Accepted-AOC L1 |
Tender Value
₹10 L
EMD Value
₹20,000
Closing Date
5 Jan 2026, 5:00 pmClosed
HOD SoECE
C Block SMVDU
Supply, Installation, Training, Testing and Commissioning of Machine Learning Based FPGA Kits for CEINC Lab at School of Electronics and Communication Engineering, SMVDU, Kakryal, Katra
2025_SM_298494_1
SMVDU/SoECE/Tenders/25/39
Open Tender
Electronics Equipment
SMVDU
Please refer Tender documents.
2 documents required · 2 mandatory
₹1,000
REGISTRAR SMVDU
₹20,000
17 Mar 2026
18 Dec 2025
6 Jan 2026
18 Dec 2025
5 Jan 2026
18 Dec 2025
Specifications of Machine Learning Based FPGA Kit are as follows:
ZYNQ Ultra Sacale ZCU104 + Evaluation Kit System Logic Cells (K) • 504 Memory • 38Mb, DSP Slices • 1,728, Video Codec Unit • 1 Maximum I/O Pins • 464, Featured Xilinx Devices ,Logic Cells 500k Memory 38Mb, • I/o Pins 464 Configuration • USB-JTAG FT4232H,• Dual Quad-SPI flash memory • MicroSD Card Memory • PS DDR4 64-bit Component, • Quad-SPI flash,• Micro SD card slot Control & I/O • 4x directional pushbuttons, • DIP switches,• PMBUS, clocks, and I2C bus switching, • USB2/3 Expansion Connectors • FMC LPC (1x GTH), • 3 PMOD connectors, • PL DDR4 SODIMM Connector – 64 bit Communication & Networking • USB-UARTs with FT4232H JTAG/3xUART Bridge • RJ-45 Ethernet connector • SATA (M.2) for SSD access Display • HDMI 2.0 video input and output (3x GTH) • DisplayPort (2x GTR) Training • One-day Vivado-based training on these boards. Power • 12V wall adaptor or ATX Clocking • Programmable clocks, System clock, user clock • Jitter attenuator
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tech_bid_open.pdf
tech_eval.pdf
fin_bid_open.pdf
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fin_eval.pdf
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BOQ_967511.xls
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