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Eligibility, documents, scope and key termsEligibility, required documents, scope of work and key terms of this tender, in one click.
| # | Company | Offered Item | Amount | Rank | Status |
|---|---|---|---|---|---|
| 1 | L1₹62.1 LQualified Make: CUSTOM
Model: VT-CUSTOM-PROJ
Title: FPGA DEVELOPMENT & EVALUATION BOARD 5 403 ANUGRAHA 17TH MAIN HAL 2ND STAGE BANGALORE KARNATAKA 560008 | BENGALURU URBAN | KARNATAKA | 560008 | Make: CUSTOM
Model: VT-CUSTOM-PROJ
Title: FPGA DEVELOPMENT & EVALUATION BOARD | L1 | Qualified MII | |
| 2 | L2₹64.2 L+₹2.1 L (3.43%)Qualified Make: NA
Model: FPGA Dev&EvalBoard
Title: FPGA DEVELOPMENT & EVALUATION BOARD VINYAS F86 BUILDING ITI LIMITED DOORAVANINAGAR BANGALORE KARNATAKA 560016 | BENGALURU URBAN | KARNATAKA | 560016 | Make: NA
Model: FPGA Dev&EvalBoard
Title: FPGA DEVELOPMENT & EVALUATION BOARD | L2 | Qualified MII | |
| 3 | L3₹67.3 L+₹5.2 L (8.29%)Qualified Make: xilinx
Model: FPGA DEVELOPMENT & EVALUATION BOARD
Title: FPGA DEVELOPMENT & EVALUATION BOARD 21 7TH MAIN 1ST BLOCK KORAMANGALA BANGALORE 560034 | BANGALORE | BENGALURU URBAN | KARNATAKA | 560034 | Make: xilinx
Model: FPGA DEVELOPMENT & EVALUATION BOARD
Title: FPGA DEVELOPMENT & EVALUATION BOARD | L3 | Qualified MII | |
| 4 | Disqualified Make: Unbrand
Model: FPGA DEVELOPMENT & EVALUATION BOARD
Title: FPGA DEVELOPMENT & EVALUATION BOARD 182 D 8 3 191 4 AILENI ARCADE MS APARNA AILENI DIRECTOR MR IVKV SHARMA DIRECTOR 182 D 8 3 191 4 AILENI ARCADE VENGALRAO NAGAR HYDERABAD VENGALRAO NAGAR | Make: Unbrand
Model: FPGA DEVELOPMENT & EVALUATION BOARD
Title: FPGA DEVELOPMENT & EVALUATION BOARD | - | Disqualified | |
| 5 | Disqualified Make: Altera
Model: FPGA DEVELOPMENT & EVALUATION BOARD
Title: FPGA DEVELOPMENT & EVALUATION BOARD 1ST MAIN 60FT ROAD OPP SHK KALYANAMANTAPA 2ND FLOOR NO 14B SRI SAMARTHA AMARJYOTHINAGAR WARD PATTEGARAPALYA BANGALORE KARNATAKA 560079 | BENGALURU URBAN | KARNATAKA | 560079 | Make: Altera
Model: FPGA DEVELOPMENT & EVALUATION BOARD
Title: FPGA DEVELOPMENT & EVALUATION BOARD | - | Disqualified |
Tender Value
Refer Docs
EMD Value
₹2.9 L
Closing Date
19 Feb 2026, 9:00 pmClosed
Eligibility, documents, scope and key termsEligibility, required documents, scope of work and key terms of this tender, in one click.
FPGA DEVELOPMENT & EVALUATION BOARD
8835537
GEM/2026/B/7107492
Two Packet Bid
FPGA DEVELOPMENT & EVALUATION BOARD
Hyderabad, Telangana
Total value wise evaluation
PRODUCT_CUSTOM
7 documents required · 7 mandatory
3 yrs
₹20 L
₹20 L
30%
| Item | Delivery Location | Qty | Delivery |
|---|---|---|---|
| FPGA DEVELOPMENT & EVALUATION BOARD | - | 1 | - |
Director, DLRL, Hyderabad, Department of Defence Research & Development, Office of DG (ECS), Ministry of Defence, DLRL, (K. Murali)
₹2.9 L
19 Feb 2026
29 Jan 2026
19 Feb 2026
Tap a document below to read it instantly. You can also download everything as a ZIP if you prefer.
bid_8835537.pdf
GEM_BID
26fps013s_2026-01-13-10-19-32_7f74c645a84eee069a33aa2d8a381de0.pdf
SPECIFICATION
26FPS013S_8652ad23-34b8-4ada-b59c1768296891280_GeM_Indentor.pdf
OTHER
list-of-categories-where-trials-are-allowed_1712126171.pdf
OTHER
gtc.pdf
OTHER
26fps013s_2026-01-13-10-19-32_7f74c645a84eee069a33aa2d8a381de0.pdf
GEM_SPEC • 0.87 MB
26FPS013S_8652ad23-34b8-4ada-b59c1768296891280_GeM_Indentor.pdf
GEM_OTHER • 0.87 MB
list-of-categories-where-trials-are-allowed_1712126171.pdf
GEM_OTHER • 0.52 MB
gtc.pdf
GEM_OTHER • 0.70 MB
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