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| # | Company | Amount | Rank | Status |
|---|---|---|---|---|
| 1 | L1₹4.8 CrAccepted-AOC | ₹4.8 Cr Quoted ₹4.9 Cr | L1 | Accepted-AOC BRING L1 |
| Sl No | Description | Qty | Unit | GAETEC SITAR L1 |
|---|---|---|---|---|
| 1.00Development Contract for VCSEL | ||||
| 1.01 | NRE Charges for Unit Process Optimization and Process Development as per specification details attached at annexure 'V' | 1 | Job | 2,10,00,000 ₹2.5 Cr |
| 1.02 | DC Test/Measurement on fabrication wafers as per specification details attached at annexure 'V' | 5 | Job | 40,00,000 ₹47.2 L |
| 1.03 | Wafer fabrication charges for 10 Product Wafers and Masks as per specification details attached at annexure 'V' | 1 | Set | 1,65,00,000 ₹1.9 Cr |
Tender Value
Refer Docs
EMD Value
₹24.5 L
Closing Date
2 Jun 2025, 2:00 pmClosed
SUNIL KUMAR SINGH, SR. STORES OFFICER-II
DRDO, SSPL, LUCKNOW ROAD, TIMARPUR, DELHI
Development Contract for VCSEL
2025_DRDO_706016_1
SPL/MM/DPP/SBM/SPL165/R/2526/4
Single
Miscellaneous Services
600 days
SSPL
Please refer Tender documents.
2 documents required · 2 mandatory
₹0
₹24.5 L
Yes
29 Jan 2026
9 May 2025
3 Jun 2025
9 May 2025
2 Jun 2025
10 May 2025
stage.html
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tech_bid_open.pdf
tech_eval.pdf
fin_bid_open.pdf
boq_comp_chart.xlsx
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fin_eval.pdf
aoc.pdf
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